This application claims priority to previously filed English language provisional application No. 60/343,737 filed Dec. 28, 2001 entitled Wireless Computer System With Queue And Scheduler, having at least one common inventor.
The present invention relates, in general, to computer systems, and more particularly, to wireless computer systems.
A wireless computer system usually is a computer system that has the capability to utilize wireless communication techniques to provide interconnectivity between a computer and elements within a network such as interconnectivity to another computer, servers, and even wired networks. One example of a wireless computer network is commonly referred to as a wireless local area network (WLAN). WLANs and other wireless computer networks provide computer users mobility and remove the constraint of having a network cable physically attached to a computer. WLANs typically are used to augment wired networks, for example, providing a WLAN coupled to a wired LAN within a building or on a campus. Because of the advantages of a WLAN, they gained strong popularity leading to a rapid expansion of the United States WLAN market. Thus, the most common implementation of a wireless computer network is a WLAN.
Most WLAN's are implemented using the Institute of Electrical and Electronic Engineers (IEEE) specification commonly known as 802.11 (IEEE 802.11 or 802.11) including IEEE 802.11b. The 802.11 specification defines some of the functional aspects of a Medium Access Control layer (MAC) and a Physical layer (PHY) that is unique to a WLAN. The MAC layer is defined to handle all management and control issues relating to mobility and the communications protocol structures, and to be transparent to higher layers of IEEE 802.X protocols. The PHY layer defines protocol structures required to support the wireless medium.
A typical implementation of a computer system incorporating a WLAN, including an 802.11 WLAN, is schematically illustrated in FIG. 1. A computer system 10 includes a host system or host 11 generally delineated by a dashed box. Host 11 has a host processor 12. Host 11 often utilizes a North Bridge controller or North Bridge 13 that controls interactions between processor 12 and critical system resources such as a system memory 15 and a display device such as a graphics display. Host 11 often also includes a South Bridge controller or South Bridge 14 that controls interactions between processor 12 and I/O devices. South Bridge 14 typically has a PCI bus 16 through which most peripherals, including a WLAN module 17, are interfaced to system 11.
WLAN module 17 typically implements the 802.11 MAC and PHY protocols. Most of the 802.11 MAC control functions are performed by a micro-processor 18 utilizing programs stored generally in a ROM 21 or other equivalent storage device. Using the program in ROM 21, processor 18 operates on data stored in WLAN module 17, typically in a RAM 19, to implement the 802.11 MAC control functions. A baseband processor 24 and a radio frequency (RF) broadband front-end or front-end 26 generally implement the PHY requirements of 802.11 including presenting data to and receiving data from processor 18, encoding and decoding data using one of the 802.11 coding schemes, determining channel busy or idle status and presenting the status to processor 18, checking the cyclic redundancy check characters (CRC), and modulating and demodulating the encoded data onto and from the channel at the 802.11 frequencies.
One problem with system 10 and particularly with WLAN module 17 is system partitioning. WLAN module 17 interfaces to host system 11 through PCI Bus 16. Typically, several other peripheral devices in addition to module 17 are also interfaced to host system 11 through PCI Bus 16. The PCI 2.0 standard specifies the protocol and timing in addition to the bus arbitration that different modules that are interfaced to PCI bus 16 must use in order to gain access to PCI Bus 16. For some wireless transmission sequences, the PCI bus latencies may be greater than the time that system 11 requires to store the data into wireless module 17, thus, the system can not provide the data in sufficient time to meet the WLAN protocol. For example, 802.11 can have a receive-transmit sequence that only allows a time period of about ten micro-seconds between receiving a frame and the next transmission time slot. Several transactions across PCI Bus 16 can be required to effect the responsive transmission. System 10 can require up to six microseconds or longer just to gain access to PCI Bus 16. Consequently, in order to minimize the throughput limitations host processor 12 preloads all of the data to be transmitted into WLAN module 17, typically into RAM 19, prior to initiating a transmission. After host processor 12 stores all the data, processor 18 reads the data from RAM 19, prepares all the headers, control, and status fields for the frame as required by the WLAN protocol, and then begins to transmit the frames to baseband processor 24 for transmission over the wireless channel. The partitioning of system 10 requires that all data be transferred into wireless module 17 prior to initiating a transmission.
Another problem with system 10 is costs. Because system 11 preloads all the data to be transmitted into WLAN module 17 prior to initiating a transmission, WLAN module 17 must have sufficient storage to accommodate the data in addition to storage for the programs stored in ROM 21, and must also have working storage in RAM 19 for the programs. A typical module 17 often requires at least one hundred twenty-eight Mega-bytes (128 M bytes) for RAM 19 and can use one hundred twenty-eight Kilo-bytes (128K bytes) for ROM 21. Some WLAN modules require additional RAM and flash memory in addition to RAM 19 and ROM 21, thereby further increasing costs.
Additionally, the partitioning of system 10 requires a dedicated microprocessor to process information prior to a transmission. The additional micro-processor further increases costs and system power dissipation.
Accordingly, it would be desirable to have a computer system and method that reduces the computer system costs, and that improves the partitioning of the system.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well known steps, flows, and elements are omitted for simplicity of the description.